1. Field of the Invention
The present invention relates to a clock recovery apparatus and method for recovering clock signals from data signals, and more particularly, to a clock recovery apparatus and method for recovering clock signals from burst mode data signals having different phases for different packets.
2. Description of the Related Art
Typically, a clock recovery apparatus incorporates a phase loop lock (PLL) circuit to recover a clock signal having the same phase with an input data signal by adjusting a control voltage of a voltage controlled oscillator (VCO) with a feedback signal to eliminate a phase difference between the clock signal generated by the VCO and the input data signal. However, it takes too long time for the typical clock recovery apparatus to synchronize the phases of the two signals, and therefore, the typical clock recovery apparatus is inapplicable to a burst mode data signal having a phase varying with every other packet. Thus, in order to recover the clock signal from the burst mode data signal, a burst mode clock recovery apparatus is required.
Conventionally, the burst mode clock recovery apparatus incorporates a plurality of gated oscillators, as shown in FIG. 1. Referring to FIG. 1, a conventional burst mode clock recovery circuit includes a plurality of gated oscillators 110 and 120, an inverter 130 for inverting an input data signal A and providing the inverted input data signal to one of the gated oscillators 110 and 120, and a NOR gate 140 for NOR operating output signals B and C of the gated oscillators 110 and 120 and outputting a NOR operated signal D.
Each of the gated oscillators 110 and 120 includes a NOR gate 112 or 122, and a delay circuit 114 or 124 for delaying the output signal B or C of the gated oscillator 112 or 122 for half of a time period of the data signal, T/2, and feeding the delayed signal back to the NOR gate 112 or 122. When the input data signal is high, each of the gated oscillators 110 and 120 outputs a low signal. When the input data signal is low, each of the gated oscillators 110 and 120 outputs a high signal for a predetermined time of T/2, and then, a low signal after the predetermined time of T/2 as the high signal is fed back to each of the NOR gates 112 and 122 through each of the delay circuits 114 and 124. If the input data signal is kept low, then the output signal of each of the gated oscillators 110 and 120 repeats high and low for every other predetermined time of T/2.
Therefore, it is possible to recover a clock signal having a time period of T using a pair of gated oscillators 110 and 120 as described above, one of which is provided with an inverted input data signal through an inverter 130, and a NOR gate 140 for adding output signals of the gated oscillators.
FIG. 2 is a timing chart of the signals for the elements included in the conventional burst mode clock recovery apparatus. As shown in FIG. 2, if the phase of the input data signal is transited, the clock signal is also transited in accordance with the phase transition of the input data signal.
The frequency of the clock signal that can be recovered by the conventional burst mode clock recovery apparatus is determined by the time difference of the input signals to the NOR gates 112 and 122 of the gated oscillators 110 and 120. Accordingly, in an ideal case where there are no time delays in the NOR gates 112 and 122, and if the time delays of the delay circuits 114 and 124 are T/2, respectively, the frequency of the recovered clock signal is 1/T.
However, since the NOR gates 112 and 122 actually lead to time delays, and the time delays induced by the NOR gates 112 and 112 become greater as the frequency of the data signal increases, the frequency of the clock signal recovered by the conventional burst mode clock recovery apparatus is limited to 1/T which can be achieved only when the NOR gates 112 and 122 are simultaneously characterized by the time delays of T/2. Therefore, the conventional burst mode clock recovery apparatus cannot be used in a high-speed packet communication system such as an optical packet switching system for processing data at a frequency of 10 GHz or higher.